Such a method may be used in, for example, the manufacture of a bipolar transistor when the buried region or layer forms part of the collector region and the device region is the base region to which the contact region makes a side wall contact. A paper entitled `Fabrication process and device characteristics of side wall base contact structure transistor using two-step oxidation of side wall surface` by Katsuyoshi Washio, Tohru Nakamura and Tetsuya Hayashida published in the IEEE transactions on Electron Devices Vol. 35 No. 10, October 1988 at pages 1596 to 1600 describes such a method of manufacturing a bipolar transistor having a side wall base contact.
As discussed in the aforementioned paper, the dimensions of the window area of the side wall through which the impurities are diffused to define the contact area is particularly important as it defines the thickness of the base region. Moreover, if the contact region is formed too close to the buried collector region then the breakdown voltage of the transistor will be reduced while the base-collector capacitance will be increased, adversely affecting the high frequency performance of the transistor.
The aforementioned paper proposes a two-step oxidation process enabling a thicker insulating region, in particular an oxide region, to be formed so that the window area and therefore the base contact region is well spaced from the buried collector region.
As described in the paper, after formation of a first silicon dioxide insulating layer on the side wall and the area of the one major surface, a first protective layer in the form of an anti-oxidation silicon nitride layer is defined on the side wall of the step, the exposed area of the one major surface is then etched to form a deeper step and the new surface area surrounding the deeper step is oxidized to form a thicker second silicon oxide layer. A second silicon nitride layer is then provided on the first silicon nitride layer and the surface again oxidised to define the final isolation silicon oxide forming the insulating region.
Although the method described in the paper spaces the relatively thick insulating region from the device area defined by the step and therefore may avoid crystal defects within the device area which may otherwise be caused by the formation of a relatively thick oxide region, the two silicon nitride protective layers influence the dimensions of the side wall window area and the generation of defects. Moreover, the method is very complex and it is admitted in the paper that control of these protective layers is particularly important and that it is essential to determine the optimum thickness for the first and second silicon nitride protective layers. Indeed, the paper presents various SEM micrographs showing the problems which may arise if the thicknesses of the first and second silicon nitride layers are not optimised.
It is an aim of the present invention to provide a method of manufacturing a semiconductor device in which the dimensions and location of the window area can be controlled or adjusted so as to avoid undesirable increases in base-collector capacitance and to avoid a reduction of breakdown voltage without having to resort to the complicated process described in the aforementioned paper.